1. Field of the Invention
The present invention relates to a semiconductor memory device which enables a test of defect sites in dynamic random access memory, for example Priority is claimed on Japanese Patent Application No. 2007-182360, filed Jul. 11, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
A memory array of dynamic random access memories (DPAMs) is configured by bit lines and word lines. Data is stored in memory cells arranged at intersections of the bit lines and the word lines. By detecting a minute potential difference which occurs on a pair of bit lines, the data is detected from the memory array. The minute potential difference occurring on the pair of bit lines is amplified and output by a sense amplifier circuit included in the DRAM.
With the recent advance of miniaturization technologies, gaps between wirings in a memory array become narrower and narrower. Due to this, defects appear such as short circuit between word lines and bit lines. One method of detecting and rejecting such short circuit defects is a test mode to expand generation intervals of word line driving sense amplifier circuit activation signals SE (hereinafter referred to as “word-SE interval expansion test”). In this test mode, the generation intervals of word line driving and sense amplifier circuit activation signals SE are expanded from several ns in normal operation up to several μs.
The word-SE interval expansion test mode will be now described with reference to FIGS. 11 and 12. FIG. 11 is a timing chart showing an operation in a normal state, where the word-SE interval expansion test is not performed. A control signal R2AC0B determines a timing at which a word line is driven. Control signals RSAEPT and RSAENT correspond to the above-mentioned sense amplifier circuit activation signal SE and cause a sense amplifier circuit to initiate an amplification operation. When an active command ACT is input, a mat array selection signal is input by an address input along with the active command and accordingly a targeted memory mat is selected. When the control signal R2AC0B is input, that is, when the control signal R2AC0B is changed from an “H (High)” state to an “L (Low)” state, the word line is driven. As described above, in the operation in the normal state, the sense amplifier circuit is activated after the lapse of several ns during which the word line is driven. Due to this, the control signals RSAEPT and RSAENT are generated by delaying the control signal R2AC0B by means of a delay element or the like, thereby activating the sense amplifier circuit.
FIG. 12 is a timing chart showing an operation in a case of word-SE interval expansion test mode. In the case of word-SE interval expansion test mode, a generation interval of an external CLK is expanded to several μs by means of a tester or the like. This delays generation of the control signals RASEPT and RSAENT to activate the sense amplifier circuit, thereby achieving the word-SE interval expansion test. Thus, as shown in FIG. 12, it can be seen that an interval between word line driving and generation of the sense amplifier circuit activation signal is further expanded as compared to FIG 11.
As the word-SE interval is expanded, a bit line detected as having a short circuit defect loses the amount of signal output from a memory cell due to leakage through the short circuited site. Therefore, when the sense amplifier circuit is activated, it is possible to detect the site having the short circuit defect and thus to reject the defect site.
In recent years, with an increase in the speed of DRAMs, due to reducing power consumption, voltage of a power unit has been lowered, such as single data rate (SDR) (3.3 V), double data rate (DDR) (2.5 V), DDR2 (1.8 V), DDR3 (1.5 V) and so on. With such lowering of voltage, the voltage of a memory cell array (hereinafter referred to as “Vary”) has also been lowered. The lowering of the Vary lowers the voltage of a gate with respect to a source of a transistor of a sense amplifier circuit in a sensing operation (hereinafter referred to as “Vgs”). This becomes the cause of a decrease in a sensing speed. If a threshold voltage of the transistor of the sense amplifier circuit is lowered in order to prevent such decrease in the sensing speed, it is known that off-current of the sense amplifier circuit is increased.
In the above-described word-SE interval expansion test, the transistor of the sense amplifier circuit is in a turn-off state for a long time after normal operation starts.
If the threshold voltage is lowered in order to prevent a decrease in the sensing speed, increased off-current flows for the expanded time. In this state, when the short circuit defect is to be detected in the word-SE interval expansion test, read data is lost due to the off-current of the transistor of the sense amplifier circuit. That is, there arises a problem that a site in which data is lost due to the off-current is also detected in addition to the short circuit defect to be originally detected.